1. Field of the Invention
The present invention relates to semiconductor processing techniques, and more particularly, to semiconductor devices and manufacture methods thereof.
2. Description of the Related Art
With the development of improved semiconductor processing techniques, the feature size of MOSFET is continuously reduced. Attention is drawn to the issue of carrier mobility reduction, and consequently several schemes of carrier mobility enhancement are proposed.
Some of such schemes realize carrier mobility enhancement through applying stress to channel regions of MOSFETs.
Through applying stress to the channel region of a MOS device to induce strains in the channel region, it is possible to influence carrier mobility. Specifically, an NMOS device is electron conductive, the larger the lattice spacing, the smaller the effectiveness of lattice scattering, and thus a larger electron mobility as well as a larger driving current can be achieved. Therefore, it is desirable to apply a tensile stress to the channel of an NMOS device to enlarge the crystal lattice. In contrast, for a PMOS device, the smaller the lattice, the larger the hole mobility, so it is desirable to apply a compressive stress to the channel of a PMOS device.
A method of applying stress to channel regions may employ the coverage stress film technique.
Through deposition of a stress film after forming silicide on a source region, a drain region and a gate, a stress can be transferred to the channel region, so that the device performance can be significantly affected. As an example of stress film, it is known that a Si3N4 film deposited by thermal chemical vapor deposition has tensile stress, while a Si3N4 film deposited by plasma chemical vapor deposition has compressive stress.
In order to simultaneously improve NMOS and PMOS device performance, tensile and compressive stress films can be deposited on NMOS and PMOS devices, respectively. For example, a tensile stress film can be deposited, and then it can be etched to remove the tensile stress film on a PMOS device, and then a compressive stress film can be deposited, followed by removing the compressive stress film on an NMOS device.
A stress proximity technique (SPT) is set forward to transfer stress into a channel region more successfully. That is, sidewall spacers on both sides of the gate are reduced in thickness before a stress film is deposited to shorten the distance between the stress film and the channel region, so that the stress in the stress film can be transferred into the channel region more effectively. Consequently, a better stress effect can be achieved.
A SPT implementation method will be described with reference to FIGS. 1A through 1E.
As shown in FIG. 1A, after performing a lightly doped region (LDD) implantation on the substrate 110 using a gate as a mask, a silicon oxide layer 130 and a silicon nitride layer 140 are deposited in sequence.
Next, as shown in FIG. 1B, the silicon oxide layer 130 and the silicon nitride layer 140 are etched to form sidewall spacers 135 and 145, after which source-drain implantation is implemented to form a source region and a drain region on opposite sides of the gate, and then an annealing process is performed.
Thereafter, a metal such as Ni or Pt is deposited on the source region, the drain region and the gate. A silicide forming process is performed to form silicide 160, as shown in FIG. 1C.
Next, as shown in FIG. 1D, the SPT is implemented through removing the sidewall spacer 145 by etching.
Then, as shown in FIG. 1E, a stress film 170 is deposited thereon.
Since the sidewall spacer 145 is removed after defining the source and drain regions with the sidewall spacer 135 and 145, the stress film 170 can be placed more closely to the channel region, so that the stress in the stress film can be transferred into the channel region more effectively.
As shown in FIG. 1D, however, during the process of removing the sidewall spacer 145, a portion of the silicide 160 formed previously may also be removed. Therefore, the SPT scheme described above results in a loss of silicide.
Hence, a new SPT implementation method capable of avoiding silicide loss is highly desired.